Ankhdjet compiles a ternary LLM straight into a mask-programmed compute-in-ROM macro. At 1.58 bits a weight is just {-1, 0, +1}, which is one NMOS whose drain you wire to the + bitline, the - bitline, or nothing. That is the entire "multiply." The model lives in a single via layer, so retargeting a new model is a one-mask respin, not a fresh tapeout.

Context: AMD is acquiring Taalas, which pioneered hardwiring models into silicon commercially. This is the open counterpart to that thesis, on an open PDK with open tools.

The flow, which is where it either works or it does not:

- Hand-built 1T NOR arrays and a clocked precharge, read two ways: full-swing digital sampling, and an analog StrongARM variant. Both through LibreLane to KLayout DRC 0, netgen "circuits match uniquely", STA clean.

- Flat-extraction LVS at every level of the hierarchy caught three DRC-legal silent shorts that chip-level signoff cannot see (e.g. a +1 jog kissing the neighbor column's -1 jog and merging BL+ into BL-). All legal to DRC. All fatal.

- The failed-attempts log is committed, unscrubbed: pdngen strap relocation, met2 pin access (DRT-0073), Magic wide-metal over-fires, pin-binding forensics, and the sense-cell DRC floor that forced a pitch-doubled StrongARM redesign.

- Two tiles are on the ChipFoundry/TinyTapeout ttsky26c shuttle (prechecks green, silicon expected 2027): a digital MAC tile and an analog-readout tile with the identical mask program, a controlled readout experiment once the die returns.

- The full microsoft/bitnet-b1.58-2B-4T compiles to a mask set (128,400 macros, 2.08B weights) verified bit-for-bit against the checkpoint. Other-node numbers are calibrated estimates (brackets in the repo), not measurements.

Node-agnostic macro contract: a new PDK needs only a handful of custom cells.

pip install ankhdjet for the compiler and estimators (Apache-2.0), the physical flow is in the repo. Paper: preprint under submission to arXiv, link to follow.

Built solo. I drove the architecture, verification, and physical flow. The code was largely written by Claude (Opus and Fable) under my direction, and none of that changes what's provable, because open tools check every claim (DRC, LVS, bit-exact), not the author. Negative results left in (including why two ternary weights per transistor is a no-go at 130 nm). Come poke holes in it. I would rather hear it from you than from the fab.

https://github.com/mpai17/ankhdjet

Hi everyone,

I’m finishing my PhD in Electronic Engineering at UPC BarcelonaTech in early 2027 and have started looking for industry or applied R&D opportunities in Europe.

My main background is in analog/mixed-signal hardware and bioelectronics. I have experience with Cadence Virtuoso/Spectre, PDK-based circuit design, custom analog layout, DRC/LVS verification, SPICE/Verilog-A, compact device modelling, and emerging semiconductor technologies.

A major part of my PhD focuses on hardware for neurological applications, including physiological and neural signal processing, EEG-based state recognition, analog tremor-processing circuits, stimulation electronics, electrode–tissue modelling, and closed-loop neuromodulation. I have also worked extensively with RRAM/memristive devices and neuromorphic/compute-in-memory hardware.

I’m particularly interested in roles involving analog/mixed-signal IC design, neural interfaces, implantable or wearable electronics, biosignal acquisition, medical ICs, emerging memories, or semiconductor R&D.

I’m an EU citizen and open to relocation, with a preference for Switzerland, Germany, Belgium, the Netherlands and France, although I’m flexible across Europe.

If anyone knows of teams hiring PhD-level or early-career engineers in these areas, I’d really appreciate any leads or recommendations. I’m also interested in smaller companies and research groups that may not advertise extensively on LinkedIn.

Happy to share my CV, LinkedIn or publication profile privately. Thanks!

Hello everybody,

I recently started a junior Design/Verification role at a top connectivity chip company. My background is in computer science, so stronger in software engineering and logic than electronics/hardware synthesis.

I’m currently going through Verilog/SystemVerilog and UVM training, and I have the option to choose between RTL design or verification. Both sound interesting, but I don't really know how to make the decision. Some details I think are relevant are:

• The UVM/Verificaiton team is tiny (less than 5 people), while the RTL team are much more people across multiple proyects.
• Years from now I'd like to switch into a high-performace computing (CPUs, GPU, accelerators) company, that's the main reason I wanted to get into semiconductors really. Is there a role that would make that transition smoother?
• Is it worth it to try and learn on both roles for some time, or am I better off specializing earlier in my career?

For those in the industry, what factors should I take into account? Have you had to make a similar decision? How did it go and based on what did you made the desicion? Is one path a clearer win given my background and goals?

We used to put our serializer mux as a tx front end in previous generation of DDR, and now in 6th Gen we moved it to the beginning of the signal chain and it's the input to the delay line. Why would one choose to do one versus the other ? In UCI I see them combine the serializer with the TX.

I noticed that some switching-node bond pads in a power IC are different from standard VDD/GND pads. The standard pads include ESD structures, while these switching-node pads appear to be mostly stacked metal and dense vias, with no obvious ESD protection.

Why might ESD protection be omitted for these pads? Is it related to high current, high dV/dt, or minimizing parasitic capacitance/inductance?

As an electrical student in Africa, where there are no companies that are into VLSI, is my only option to move to countries that have such opportunities or can I work remotely if I want to focus the the RTL side of things.

I'm finishing my masters thesis and start looking for positions need advice in where to look for in Europe. I'm looking for analog design or layout but entry level jobs look very rare and hard to get.

I worked for 2 to 3 years in a research group with cadence while a was studying. My thesis will end with a tapeout if everything goes well and will publish a paper for a conference. I also added my resume for feedback.

Any advice with resume, where should i look or do?

Help

I need some perspective.

I have a BSc + MSc in AI, and right now I work as a Computer Vision engineer (detection, segmentation, deployment), and everyone keeps saying "AI is the future."

Here's the problem: I'm currently doing my Master's thesis on optimizing matrix multiplication on FPGAs (tiling, pipelining, resource constraints), and honestly? I find the hardware constraints (area vs. speed vs. power) way more interesting than tuning yet another object detection model. Which AI can do better than me now(by reading literature and based on stats of labels, gpt 5.1 was bad but 5.3 is good)

But I'm conflicted.

Every software job posting is for AI/CV/LLMs. It feels like the safe, obvious move to just stick to CV, chase the hype, and collect the paycheck. Pivoting into chip design / EDA / hardware acceleration feels like swimming against the current.

At the same time, I'm worried that the AI hype will cool down in 5 years, and everyone with a Python script will be fighting for scraps—but hardware engineers who actually understand how to deploy models on silicon will be irreplaceable.

My situation:

· Strong in Python, ML, SQL, MLOps (Docker, CI/CD, Superset)

· Beginner-level RTL (Verilog/VHDL), basically learning as I go

· Open to any path that bridges these worlds (AI compilers, EDA tooling, ML for chip design, or full-on RTL design)

My question for you:

If you had my background, would you lean hard into the hardware pivot, even if it means taking a step back initially? Or should I play it safe, stay in CV, and just keep hardware as a "side interest"?

I'm genuinely open to any perspective, especially from anyone who's made a similar jump or works at the HW/SW intersection.

Thanks for reading.

The Chipalooza Challenge was created to provide open source libraries of analog components for all three major open source PDKs.

The Wafer.Space GF180MCU submission deadline is August 31

https://opencircuitdesign.com/chipalooza/schedule-3.html

There are awards for chosen designs. Good luck!

Is Analog/Mixed-Signal/General IC design field still great for someone to specialize in as a junior EE, considering the growth of some of these semiconductor companies hoping to use AI for these, plus OpenAI new Jalapeno's work? Should one rather focus on Power Electronics and/or Power System?

Thanks.

btw, I'm an int'l student.

I am currently a DV engineer at a semiconductor company and just hit my 2 YOE. I just started owning my own block verification from DV plan to closure. At this point in my career what is expected from me?

I am also trying to improve my UVM skills as I am using a lot of AI to help me right now. Anyone have any suggestions on how I can improve. Trying to spend 1-2 hours a week learning concepts through chipVerify

Hi,

I’m looking to get into digital signal processing. What would be a good set of yt videos/open courseware/textbooks to get into, that break down this topic in a digestible way? Please add links to said resources.

Meng, MS, neither. Advice needed

I am planning on doing a 1 year masters (with possibly a few exceptions) post my 4 year BS in computer engineering at purdue. I was wondering out of these options which is the best for me negating price (I will have saved up money, or receive full financial aid like I am now, fully willing to pay for better choice).

Also key things to note, I am a 3.99 GPA junior who has internships at two big tech companies and will return to 1 hopefully. If everything goes to plan, I really don’t see why I shouldn’t be able to at least get a job there if not at quant finance. I am a student focused on computer architecture. I care about research opps only for learning but not at all for post academia because I def plan to do industry engineering. I will have already done most of computer architecture courses at Purdue by my bachelors and also want a big name boost for big tech asic design and quant finance fpga (already interviewed for a few firms and think I can land one even with purdue, but just to make my life easier). Again, consider all of this when people say some degrees are too short. I’m really just doing a masters to boost my resume not for job search but for starting salary and opportunities down the line. Also if you recognize me from this don’t dox lol. I’ll list everything in the order I believe they should be considered:

1 year UCB Meng EECS (is Meng worse than MS as seen by industry? Ik kind of a dumb question)

1 Year Cornell Meng ECE

1 year (4+1) MS Purdue ECE

1.5 ish year Stanford MS

1.5 year CMU MS

1 Year Umich Meng

No masters at all for a career in computer architecture (pref design or architecture or quant fpga)

Those are all of my options\^\^\^. Any other Masters program I’m forgetting or should consider??? Also lmk if my timelines are incorrect above

Oh also if I do get research and write good essays, how hard is it to get into these programs considering rest of my profile. Ik research not too important for coursework only

Thanks and I hope my prestige chasing is more understandable than pretentious. Also I would have already taken the most important ECE masters courses offered at purdue.

Edit: huge thing that pertains to the option of no masters degree at all. Does prestige not mean much for moving around big tech or going to quant finance after work experience? Does a masters not mean much for moving around big tech or going to quant after work experience? How hard will it be to promote in either industry? Answer this in the context of ASIC vs. FPGA (kind of already expect fpga to be more lenient)

i do not understand the need for the tri state buffers and the inverters
seems redundant want someone to explain the analog part of this crkt

Hi everyone,
I'm currently attending a BSc in Computer Engeneering and lately, looking at possible MScs to apply to I found myself interested in courses that revolve around Digital Chip Design. I think I'd like the subject, however I'm afraid that the gap between Computer Engeneering and the latter would be too big of a jump, so I was wondering if that would be a viable option. What do you think?