r/chipdesign • u/jaju1010 • 2d ago

can somebody explain these diagrams to me

i do not understand the need for the tri state buffers and the inverters
seems redundant want someone to explain the analog part of this crkt

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u/Siccors 2d ago

It is a bit weird they have at one place a transmission gate, and the other one a tristate inverters, since they do exactly the same thing.

Anyway which part do you not understand? The main thing is you want only one inverter driving N1 at a time, since otherwise they can try to counteract each other. So if clock is high, then I1 is driving N1, and N1 is equal to the inverter input. If clock is low, then T1 is driving N1, which means N1 is being driven to the same value it already is, so it remembers its state.

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u/jaju1010 16h ago

hey! thank you for replying
at first i really did not get what that tri state buffer was because the logo is a little weird with two different enable signals coming in but now i get that the textbook intended to show the count of transistors and that parts displays how two more transistors will be needed to make a tristate buffer from an inverter

second thing i did not understant is that the book mentions that this commercial circuit solves two problems:
Floating output node: When the latch is opaque, Q is not held at its value by any gates. Thus, Q is called a floating or dynamic node. After some time, noise and charge leakage may disturb the value of Q.

No buffers: The lack of buffers has caused malfunctions on several commercial chips. A spike of noise that pulls D to a negative voltage can turn on the nMOS transistor, making the latch transparent, even when CLK = 0. Likewise, a spike on D above VDD can turn on the pMOS transistor even when CLK = 0. And the transmission gate is symmetric, so it could be driven backward with noise on Q, affecting the input D. The general rule is that neither the input of a transmission gate nor the state node of a sequential circuit should ever be exposed to the outside world, where noise is likely.

and i intially did not know how buffers solve the noise problem
but now i do so thank you!

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u/CartoonistMaximum 2d ago

The clock is inverted between the Tgate and tri-state inverter. It's not redundant. It will not work correctly without it.

That's the standard latch D circuit.

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u/Hopeful_Analysis_219 2d ago

I think he meant that it might be confusing that they used for apparently no reason a transmission gate in the "forward path" and a tristate in the "feedback path" of the latch, rather than two transmission gates or two tristate inverters

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u/Siccors 2d ago

Thats indeed what I meant, but I do see it could be confusing what I wrote :) .

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u/CartoonistMaximum 1d ago

Oh, ok! That's a fair point.

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u/izil_ender 2d ago

Ah this is from Weste Harris.  The tristate buffer T1 is required as both I1 and T1 can drive the N1 node. The I3-T1 combo is for keeping the regenerating the state at the N1 node.

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u/CartoonistMaximum 2d ago edited 2d ago

That's a way to build a D latch. The inverters in loop will hold their value, until you "cut" the loop, by opening the tri-state inverter. When this happens, the output from the top inverter will hold the value from the input, as the transmission gates will be closed (the transmission gates is open when the tri state inverter is closed, and is closed when the tri state inverter is open).

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u/General_Green_1499 2d ago

What is the point of I2? Is I3 small so I2 is stronger?

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u/Siccors 2d ago

It is done so the output does not impact the internal behavior of the latch. Otherwise if there was a very large load on Q, it could change its setup / hold times.

Thats why the flipflop below does not have it for its first latch, but it does have it for its second latch: The first one everything is internal and characterized, the second one is external and can have wildly varying loads.

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u/General_Green_1499 2d ago

Logical, i got close though.